1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus.
2. Description of Related Art
Conventionally various methods for developing a semiconductor integrated circuit apparatus have been proposed. Among those methods, there is a technique called structured ASIC (Application Specific Integrated Circuit). The structured ASIC has a common wiring layer and a customized layer. The common wiring layer is a wiring layer not dependent on a user circuit and common to several sorts. The customized layer is provided over the common wiring layer to form the user circuit. In the customized layer, the functional cell is wired to realize the user circuit. Note that the functional cell is a cell constituted of the common wiring layer and an underlying basic device layer (transistor layer).
As shown in Japanese Patent Publication No. 3555080, a circuit configured with changeable functions (general-purpose logic module or a general-purpose logic cell or the like) is used as a functional cell. Examples of such circuits include NAND, NOR, EXOR and EXNOR.
According to this technique, a mask to form the common wiring layer can be used in common, thus the development cost can be reduced. Further, regardless of a user request, the functional cell can be previously prepared in the common wiring layer. Therefore, layers from the basic device layer to the common wiring layer are prepared as a “foundation” to create the customized layer and layers above in response to a user request. Thus the development period can be shortened.
An example of a semiconductor integrated circuit apparatus constituted by the structured ASIC is described hereinafter in detail. FIG. 12 is a view showing a configuration example of a clock synchronous circuit. As shown in FIG. 12, a combinational circuit 2 constituting a desired logic is formed between flip-flops 1. Generally in a semiconductor integrated circuit apparatus, a circuit is constituted of a sequential circuit like the flip-flop 1 and the combinational circuit 2.
In a GA (Gate Array) that wires according to a user circuit, the sequential circuit such as the flip-flop 1 and combinational circuit 2 can be optimally configured using a common basic device layer formed by arranging same transistors.
On the other hand in the structured ASIC, if a functional cell configured with changeable functions is used for a sequential circuit such as the flip-flop 1 and also for the combinational circuit 2, the size of the circuit for the functional cell increases, thereby reducing the capacity of the user circuit.
Further, even if the functional cells with changeable functions is prepared as a combinational circuit to configure the sequential circuit by combining the combinational circuit, the circuit size increases as compared to the circuit designed for the sequential circuit, thereby reducing the capacity of the user circuit.
Accordingly the sequential circuit like the flip-flop 1 is generally prepared as a different functional cell from the functional cell for a combinational circuit.
With such background, in the structured ASIC, two kinds of functional cells are previously prepared; a functional cell constituting a sequential circuit including the flip-flop 1 and a functional cell constituting the combinational circuit 2 other than the sequential circuit.
FIG. 13 is a view showing an example of a conventional circuit arrangement disclosed in Japanese Unexamined Patent Application Publication No. 64-41326. As shown in FIG. 13, flip-flops (FF) 1 and programmable logic array (PLA) units 2 are placed side by side in the same rows in an internal circuit area (wiring area) of a substrate 5. The rows having the flip-flop 1 and programmable logic array (PLA) unit 2 are placed alternately in the row direction. Input/output units 3 are placed around the internal circuit area 4. The circuits disclosed in Japanese Unexamined Patent Application Publication No. 11-17014 and Japanese Unexamined Patent Application Publication No. 2-29124 has similar circuit arrangement. As disclosed therein, in a conventional semiconductor integrated circuit apparatus, the flip-flop 1 and combinational circuit 2 are placed in the same row or column.
As shown in FIG. 13, the PLA units 2 and flip-flops 1 are placed alternately, as in PLA unit 2-11, flip-flop 1-11, PLA unit 2-12, flip-flop 1-12 . . . flip-flop 101n. Accordingly as indicated with the right directed arrow in FIG. 13, with the signals passing in the right direction of the chip, detouring the lines in other columns is unlikely to be generated. However in relation to problems on the interface, lines may be wired in the upward direction, not right direction. In such case as indicated with the upward arrow in FIG. 13, lines are likely to be detoured in other rows as in PLA unit 2-m2, PLA unit 2-32, flip-flop 1-32, PLA unit 2-32, PLA unit 2-22, flip-flop 1-22, PLA unit 2-22 and PLA unit 2-12.
A case of providing a plurality of signal lines having the same functions such as a bus signal is shown in FIG. 14A. In this case, signals pass to the right direction via circuit including a combinational circuit 21. In such case, logical function of the flip-flop 1 and between the flip-flops 1 in each of the signal lines is configured in the same way. However there are cases that a signal line needs to bend in a right angle halfway. In such case as shown in FIG. 14B, signal lines positioned at the outer side are longer than signal lines positioned at the inner side. Specifically, depending on the position of the signal line, the length of the signal line varies, thereby generating a delay between a plurality of signal lines. Further as shown in FIG. 14B, in the portion P where signal lines bend upwards when viewed from the front, the signal lines are concentrated. Specifically, congested lines require countermeasures including detouring lines.